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F
ew years ago, an RF test engineer would have been very focused in his very unique field, performing tests on discrete RF devices such as mixers, power amplifiers, low noise amplifiers and RF switches. Today, the test industry faces increasing levels of integration such that many of these discrete device functions ar used as building blocks and are contained within one chip or module.

Furthermore, the integration levels are such that system-on-a-chip(SOC) devices contain baseband(analog) functionality as well as digital functionality. Earlier RF devices often contained three-wire serial communications for controlling things such as gain control, but current digital functionality of these devicesis becoming complex.

SOC devices are those that have more than one of the discrete RF devices (such as LNA, PA, Mixer, RF switch, VGA, Baseband/IF modulator/demodulator, Transmitter, Receiver and Transceiver) combined on a substrate to provide some function, for example, placing all of the said devices that make-up a mobile phone handset onto a single microchip. Over the past few years, there have been many attempts to place the complete wireless radio on a chip, but for practical reasons, what is termed SOC is often only a portion, such as that comprising the input/output at the antenna down to the analog baseband input/output on a wireless transceiver. Thus, an exception to the above statement is that a discrete transmitter, receiver, or transceiver may also be term as an SOC device.

The recent trends have been moving toward much higher levels of integration. This is primarily due to two reasons: reduced-cost at the consumer level and the desire for reduced power consumption (longer battery life). It is apparent that lower-frequency analog and lower-level digital functionality is core-siding on the SOC chip with RF front-end devices. This trend will continue as pressures to achieve the above two goals surmount. Below is an of RF SOC block diagram with higher level of integration.
SOC devices, as used in this discussion, have atleast one RF input(or output). Based on that, SOC devices for wireless communications can be broken down into the following types, based on input/output configuration: RF/RF; RF/IF; RF/baseband; and RF/Digital.

RF/RF and RF/IF are treated similarly with respect to testing procedures. The measurement techniques for IF frequencies still require attention to detail and an understanding of making measurements at high frequencies where traditional Ohm's Law-based calculations will not work. Examples of these types of SOC devices would include a chip consisting of a filter/LNA combination or filter/LNA/mixer combination to be used as the front-end-receiver. Additionally, they may have some digital signals for received signal strength indicator (RSSI) or automatic gain control(AGC).

RF/baseband SOC devices are used quite commonly today in WLAN modems. They may contain everything from the input filter/LNA all the way to the in-phase, quadrature (IQ) outputs. When testing these devices, the test engineer must have an understanding of RF measurement techniques, which are based on the frequency domain and time domain. RF/digital SOC devices are used quite commonly today in Bluetooth modems. The reason for this is that the bluetooth architecture is relatively simple to implement on a single chip. It has been explored quite exhausitively, and as a result the low cost pushes a minimum number of chips to be used in a bluetooth modem.

That's all for now. Stay tune on my next articles as I'm giving some few details on the RF discrete devices being mentioned.

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by: Allan B. Dizon
The supply current (IDD) tests verify that the DUT supply current is not excessive. Although it is usually not specified, it is sometimes good practice to check for a minimum supply current. There are two methods for testing the device supply current. The first method is called static testing, because the device is not active. The second method is called dynamic testing, because the device is active while the current is being measured. Because the instruments for measuring DC vakues are slow in comparison to typical device execution speeds, dynamic testing usually makes use of a functional test loop. The device runs the same sequence repeatedly until the DC measurement is complete.


The IDD current can be measured once the device is in the specified condition. It is usually good practice to plan for settling time delay after the conditions are programmed and before making the measurements. There are some factors that may prevent the device from reaching the specified condition immediately, particularly the loadboard bypass capacitors and the settling time of the ATE system instruments.


As a suggestion, here's the general test sequence for a DUT:

• Force all input pins to 0 volts
• Force all output pins to 0 mA
• Force VDD to +12.0 volts
• Force VEE to - 12.0 volts
• Wait for the ATE instruments and DUT to settle
• Measure IDD current and compare with limits
• Measure IEE current and compare with limits

S
ignal Pin Leakage is a customer-specified that needs to be guaranteed by test. It is also the best way to detect ESD/EOS damage caused by part handling during the manufacturing process. Historically, leakage has been useful in highlighting flaws in the wafer/assembly process. The goal of this test is to screen for fab process excursions, assembly defects and damage caused by back-end manufacturing handing while guaranteeing the customer published specifications. As such, leakage is a quality and reliability-required screen.

by: Allan B. Dizon

The continuity test (also called contact test) verifies that, during a device test, electrical contact is made to all signal pins on the DUT and that no signal pin is shorted to another signal pin or power/ground. Device cost is directly related to how long it takes to test each device. One of the best ways to reduce average test time per device is to reject bad devices as soon as possible. The continuity test determines very quickly whether a device has shorted pins, or missing bond wires, a pin damaged from static electricity, a manufacturing defect, etc. It can also point to test system related problems such as wafer probe card or a device test socket which is not making good contact.

Test conditions for a continuity test are not normally defined in the device specification or data sheet, but there are standard values which apply to most standard device types. These standards values are presented in the guidelines here:

• To test for continuity , first ground all device pins including power and ground pins. Next connect the Parametric Measurement Unit (PMU) to a single device pin and force a current which will forward bias one of the protection diodes (see figure 1). A negative current will forward bias the the diode to ground; a positive current will forward bias the diode to VDD. A current in the range of 100uA and 500uA should be adequate. Once forward biased, the voltage drop across the protection structure can be sensed (typically 0.65v). The sensed voltage may change between various technologies and designs, but 0.65v is good for all silicon based devices.

Figure 1

• Since the PMU will be programmed to force current, a voltage clamp must be programmed to limit the voltage produced when an open pin is tested. A typical clamp value for the continuity test 3v. When an open pin is tested, the measured result is will be the clamp voltage(3v).
• To test the upper diode, which is connected to VDD, use the PMU to force a positive current of approximately +100uA. Set the upper test limit to fail if the measured result is less than 0.2v to detect short. This test method is used to test signal pins(input and output) but not power pins such as VDD or VSS.
• To test the lower diode, which is connected to VSS or ground, use the PMU to force a positive current of approximately -100uA. Set the lower limit to fail if the measured result is less than -1.5v to detect an open.
• Power and ground pins may also be tested for an open condition, but their structure is different from that of a signal pin. Test the power pins, observe the measured value on a good device, and set the test limits accordingly.
  
  

by Allan B. Dizon
First, find out what's failing, turn on the datalogger and look closely at the test results. Which test is failing, is it a DC fail, an AC fail or a functional fail? Is only one test failing, one pin failing? These are the common basic questions that need to be answer first before "deep-diving" the problem. Look for basic clues - if problem is not apparent, proceed as follows and remember to solve one problem at a time.

• Re-run the loadboard test(usually loadboard calibration or TDR - time domain reflectometry) and hardware diagnostics of the ATE. Continue on fail if the hardware is working. It may also be helpful to remove and reseat the loadboard before re-running the diagnostics.
• Get a known good device (KGD), correlation units or sometimes called golden units and test it. Are the results the same? Has the failing product been successfully tested on this test system before?
• If possible, test the device on a different test system. If the results are the same, it is not a test system problem. If the device passes, contact the test maintenance department and explain the problem seen on the first test system.
• The device will not function correctly if the opens and shorts test is failing. If a number of tests are failing get the opens and shorts test to work first.

A good way to start the investigation is to datalog the test results to a printer or file so that they can be studied. Don't waste expensive tester time viewing results on the video display if you can do it off-line. Datalog all DC and functional pass/fail measurements.

Look carefully at the results of all tests, both passing and failing. There are often helpful clues in the datalog information. Is the device drawing the correctamount of IDD current? Are the leakage tests passing? Are the VOL/VOH voltage correct? If the failures is a DC measurement, see if the failure is just over the limit or if it is a catastrophic failure.

Verify that the test has worked in the past. Are there datalogs showing the results of a successful test? If so, compare the results of all tests.

Make sure that both the test program and the failing device are the correct revisions. If the hardware passes the diagnostics, the standard device fails the same, the parts and the test program are of the correct revision, pick one test and find out why it is failing. Start by getting an oscilloscope and a DVM. Breakpoint or pause on the failing test and verify that VDD and the input levels are correct. Verify that all timings are correct. Be sure to look at every device pin with oscilloscope, look for noise or levels that appear to be incorrect.

Relax the test parameters to make it easier for the device to pass. Relax VIL/VIH/VOL/VOH and test the device again. Relax the timing parameters (use the scale factor). Test the device again and see if the results change.

It is good idea to limit the number of hours spent debugging one problem. It is an individual choice, but a good rule of thumb is do not spend more than two or three hours working on the test system on a single problem. If you work more that several hourson a single problem, stop take a break, and discuss the issue with your mentor or colleague.

Each ATE systems offer a couple of debugging tools for engineers. Most test systems have some method of looping on a functional test vector pattern and providing a means of creating a sync marker at a selected vector memory location. The test pattern can be started and stopped at any point within the vector set and failures can be ignored. The oscilloscope can be used to verfy the proper timing and voltage levels when verifying a new test program or for investigating test problems. It is absolutely essential to become proficient at using this debug technique.

Shmoo plots are useful fo debugging test holes and for finding the pass/fail limits of device operation. It can be executed from the tester keyboard or from within the test program. This tool is very useful in developing device characterization programs and collecting data for both DC and functional tests.

Search tool performs either a binary or linear search for both DC and functional tests. This tool provides a means to take a quick look at input and output thresholds, or it can be used to provide accurate measurements of device timings. It is also very useful in developing device characterization programs.

Tester resource settings can be read and modified directly from the workstation keyboard. Power supplies, input references, comparator values, timings and functional data can all be manipulated. To debug a test problem, make a breakpoint on the failing test and modify the appropriate parameters. The execute button can be use to verify the results of the modification. An oscilloscope can be used to verify pass/fail results. Become familiar with all of the tester tools - the way will greatly enhance your ability to debug and resolve problems quickly.

by: Allan B. Dizon
The following set of rules will apply in most instances. If you should ever feel a need to intentionally violate these rules make certain that you fully understand the consequences.

a. Never functionally test an input pin as if it were an output. This can be accomplished by accidentally setting the output compare mask on an input pin.

b. Never connect a tester pin driver to an output pin of a DUT. The result of this action will cause the test system and the device pin to both drive voltage and current at the same point, at the same time.

c. Never float an input pin. A valid logic 0 or 1 level must always be supplied to an input. Floating CMOS inputs may result in the device latching-up and cathastropic failures.

d. Never supply a voltage which is above VDD or below ground to an input pin or output pin. This may cause a CMOS device latchup.

e. Always, when forcing voltage, set a current clamp to limit the amount of current provided by the test system.

f. Always, when forcing current, set a voltage clamp to limit the amount of voltage provided by the test system.

g. Never change a force or sense range of the tester when directly connected to a device pin.

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I would like to share with you the commonly used terminologies in IC Test Development Engineering. Hope this would help to the aspiring Test Engineers and could serve as a refresher to all Test Engineers out there.

1. Test Program - the purpose of a semiconductor test program is to control the test hardware (such us ATE or test loadboard) in a manner that will guarantee that the DUT meets or exceeds all of its design parameters. The design parameters are defined in details from the device specification, commonly known as data sheet. The test program is often segmented into various parts such as DC Tests, functional tests and AC tests. DC testing verifies voltage and current parameters. Functional testing verifies correct operation of the various logical functions of the device. AC testing verifies that the device can perform the logical operations with specified timing constraints.

2. Input Pin - a device pin that acts as a buffer between external signals and the internal logic of a device. The input senses the voltage which is applied to it and transmits a logic 0 or logic 1 level to the internal logic of the device.

3. Output Pin - a device pin that acts as a buffer between the internal logic of a device and the external environment. An output pin is capable of providing the correct voltages to produce logic 0 or logic 1 level and also supplies the IOL/IOH current. I will explain these terms later.

4. Tri-State Output - a device pin that functions as an output pin but has the added capability of turning off (going to a high impedance state).

5. Bi-directional (I/O) pin - a device pin that functions as an input, an output and also capable of turning-off (going to a high impedance state).

6. Power Pin - a device pin that is connected to a power supply or ground. VDD and VCC are typical examples of a power pins. VSS and ground are also identified as power pins. Power pins have a structure that is different from signal pins.

7. Pin Electronics - circuitry located in the test head that is used to supply input signals to the DUT and receive output signals from the DUT. The pin electronics are also called PE cards.

8. Drivers - the circuitry on the pin PE card which supplies the logic 0 and logic 1 levels to the DUT. A pin is said to be driven if the test system driver applies a voltage to it.

9. Signal Format - the wave shape of an input signal supplied by the pin electronics driver circuitry.

10. Comparators - the circuitry located on the pin electronics card which senses the logic 0 and logic 1 levels from the DUT. The comparators are used during functional testing.

11. Output Sampling - the point in time at which the output signal of a DUT will be evaluated. The comparator circuitry will comparethe output voltage to a pre-defined logic 1 or logic 0 level. The test system(ATE) will then make a pass or fail decision (commonly called binning).

12. Output Mask - a method of enabling or disabling an output comparison for a tester channel during a functional test.

13. Dynamic Loads - the circuitry located on the pin electronics card which acts as a load and can be programmed to supply positive and negative currents. The dynamic load are also reffered to as programmable current loads.

14. VREF - the reference voltage associated with the dynamic loads. It controls the switching point of IOL and IOH currents.

15. PMU - precision measurements unit, also called parametric measurements unit is used to make accurate DC measurements. It is capable of forcing voltage and measuring current or vice versa.

16. Clamps - hardware which limits the amount of voltage or current that is supplied by the test system during a test. Clamps are used to protect the test operator, the test hardware and the DUT.

17. Sink - term used to describe current flow from the test system into a device output pin(positive current). When an output is in the logic 0 state it can accept current from the test system which will flow through the device to ground.

18. Source - term used to describe current flow from a device output pin into the test system(negative current). When an output is in the logic 1 state it can supply current which will flow from the DUT into the test system.

19. DPS - device power supplies are used to supply voltage & current directly to the DUT. The VDD(power) pin of the DUT will usually be connected to a DPS.

20. Test Cycle - the time duration of one test vector execution. It is based on the operating frequency of the DUT. It can be determined by the formula: Cycle = 1/frequency. It is also known as period.

21. Test Vectors - a representation of the states of inputs and outputs for the various logical functions that the device is designed to perform. Input data is supplied to the DUT by the test system. Output vector data is compared against the response from the output pins of the DUT.
Test vectors are also called test patterns or truth tables. They are often represented as a sequence of ones and zeroes or other characters which represent logical levels.

22. Vectory memory - a high speed memory which stores test vector information. Vector memory may also be called pattern memory.

23. FDATA - formatted vector data (logic 1s and 0s) combined with timing and signal format information.

24. Tester Channel - circuitry on the pin electronics card which applies and/or process voltage, current and timing for one DUT pin. Also called tester pin.

25. VIH - voltage in high is the voltage value applied to an input when when applyinga logic 1. The VIH value represents the minimum guaranteed voltage value that can be applied to an input and still be recognized as a logic 1 by the DUT.

26. VIL - voltage in low is the voltage value applied to an input when applying a logic 0. The VIL value represents the maximum guaranteed voltage value that can be applied to an input and still be recognized as a logic 0 by the DUT circuitry.

27. IIH - input leakage high is the maximum amount of current that is allowed to flow into an input when a low voltage value is forced onto the pin.

28. VOH - voltage out high is the voltage value produced by an output when driving a logic 1. The VOH represents the minimum guaranteed voltage value tha will be produced by the output when driving out logic 1.

29.VOL - voltage out low is the voltage value produced by an output when drving a logic 0.
The VOL represents the maximum guaranteed voltage value that will be produced by the output when driving out logic 0.

30. IOH - current out high is the amount of current that an output must source when driving a logic 1. The output must be capable of supplying the specified IOH current while maintaining the correct VOH voltage.

31. IOL - current out low is the amount of current that an output must sink when driving a logic 0. The output must be capable of accepting the specified IOL current while maintaining the correct VOL voltage.

32. IOZH -output high impedance leakage current high is the maximum amount of current that is allowed to flow when a high voltage is applied to a bi-directional or tri-state pin, and the pin is in the off or high Z-state.

33. Gross Testing - performing a test with relaxed conditions (levels and timings) usually made to verify if the device is "functionally alive" without regards to the test specification.

34. Wafer Sort - testing of individual devices(dice) when they are still in wafer form. This is the first attempt at separating the good die from the bad.

35. Package/Final Test - wafers are cut into individual die and each die is then assembled into package form (dual-inline package, QFP, BGA, flip chip, etc). The package device is then tested to ensure that the assembly process was correctly performd and to verify that the device still meets its design specifications.

36. QA Test - quality assurance testing is performed on a sample basis to ensure that the package test was performed correctly.

37. Binning - a means of categorizing or sorting the tested devices into their appropriate groupings, either hardware or software bins.

38. Preconditioning - setting a device into the proper logic state so that a test may then be performed. A functional vector sequence is often required in order to prepare the DUT for a DC test.

39. Static - this term indicates that the DUT is in a non-active condition, no input or output signals are changing.

40. Dynamic - a term used to indicate that the DUT is actively changing states, dynamic tests are associated with executing functional test vectors.

41. I/O Switching -the DUT alternates between receiving data from the test system (reading data) and applying data to the test system(writing data). The same pin or set of pins functions as both inputs and outputs.

42. Bus contention - a condition that exists when the test system and the DUT are simultaneously driving voltage into the same tester channel.

43. Hot Switching - occurs when a relay is opened while current is flowing through it, or when current immediately begins to flow after a relay is closed (i.e. when the two terminals of a relay are at different voltages when the relay is closed). Opening or closing a relay while current is flowing throught it may result in damage to the relay. This can be avoided through careful test programming/coding.

44. Latch Up - a high current conditions which exists within a CMOS device caused by applying an improper voltage level to a signal pin or by an improper voltage applied to VDD or ground. This condition can weaken the device or cause a catastrophic failure.

45. Glitch - when a signal level abruptly change its voltage (an/or logic) level for a very short time. Sometimes called spike.

That's the most commonly used terms in test engineering or test development engineering activities.

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T
here are a lot of Test Engineers working in electronics or in semiconductor technology companies. But did you ask your self who you really are? In what way you can contribute to your organization?

Perhaps this would be a good time to discuss the traditional roles of test engineers. But before jumping into that perspective lets take a classical scenario during new product introduction(NPI) phase to understand better the whole process.

A new semiconductor product typically begins in one of two ways. Either a customer requests a particular type of product to fill a specific requirement, or a marketing organization realizes an opportunity to produce a product that the market needs. In either case, systems engineers help define the technical requirements of the new product so that it will operate correctly in the end-equipment applications. The systems engineers are responsible for defining and documenting the customer's requirements so that the rest of the engineering team can design the product and successfully release it to production.

After the systems engineers have defines the product's technical requirements, design engineers develop the corresponding integrated circuit. Hopefully, the new design meets the technical requirements of the customer's application. Unfortunately, integrated circuits sometimes fail to meet the customer's needs. The failure maybe due to a fabrication defect or it may be due to a flaw or weakness in the circuit's design. These failures must be detected before the product is shipped to the customer.

The Test Engineer's role is to generate hardware and software that will be used by automated test equipment (ATE) to guarantee the performance of each device after it is fabricated. The test software (usually called test program) directs the ATE tester to apply a variety of electrical stimuli (such as digital signals and sine waves) to the device under test (DUT). The ATE tester then observes the DUT's response to the various test stimuli to determine whether the device is good or bad.

Sometimes the test engineer is also responsible for developing hardwareand software that modifies the structure of the semiconductor die to adjust parameters like DC offset and AC gain, or to compensate for grotesque manufacturing defects. Despite claims that production testing adds no value, this is one way in which the testing process can actually enhance the quality of the individual ICs. Circuit modifications can be made in a number of ways, including laser trimming, fuse blowing and writing to non-volatile memory(NVM) cells.

The test engineer is also reponsible for reducing the cost of testing through test time reductions and other cost-savings measures. The test cost reduction responsibility is shared with the product engineer. The product engineer's primary role is to support the production of the new device as it matures and proceeds to profitable volume production. The product engineer helps identify and correct process defects, design defects and tester hardware/software defects.

Sometimes the product engineering function is combined with the test engineering function, forming a single test/product engineering position. The advantage of the combined job function is that the product engineering portion of the job can be performed with a much more thorough understading of the device and test program details. The disadvantage is that the product engineering responsibilities may interfere with the ability of the engineer to become an expert on the use of the complex test equipment. The choice of combined versus divided job functions is highly dependent on the needs of each organization.

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A
utomatic Test Equipment(a.k.a. ATE) is a consequence of computers being interface with digitally-controlled stimulus and measurement instrumentation. ATE replaced the benchtop set-ups of instrumentation that were manually controlled to make measurements. Once started, ATE can continue its operation with no outside intervention and can test thousands of parameters in seconds.

ATE dramatically improves throuhgput and measurement accuracy. It can correct its own errors by comparing its measurements results to a known standard and compensating for the difference. It relieves workers of monotonous tasks by routinely repeating complex tests over and over again. It has inherent data processing capability. ATE doesn't make mistakes when recording test data, usually doesn't compromise a test, doesn't forget tests, and doesn't get tired. ATE has revolutionized the semiconductor industry.

History of ATE
Semiconductor ATE had its beginning, as one might expect, in the same place that semiconductors were first produced in quality. Fairchild Semiconductor recognized the need to automate the test process. Tests on transistors were performed with a separate bench set-up of instrumentation for each type of test. This was a long and tedious process. Each test required that the device be inserted into a different test set-up. It was soon realized tha if the device could be tested with a single insertion, the cost of testing could be reduced.

Fairchild's first ATE, the Model 300, was built by the newly formed Instrumentation Division. It considered of a set of different force and measuring units that were constant voltage and current sources. Plug-in cards were used to connect the various instrumentation to the relevant device-under-test(DUT) terminals. An automatic sequencer selected the proper plug-in cards in the sequence in which they were inserted into the tester. All programming was done by resistor selection on the plug-in cards. To make effective use of the Model 300, the test engineer literally had to make resistors. A plug board was used for direct classification of the devices into various pass and fail bins, depending on the test result. Although primitive, it worked. That was 1960. Not long after, a company was formed in Boston with a charter to develop semiconductor ATE. The company was called Teradyne, and with its inception the ATE industry was born.

With the advent of integrated circuits, Fairchild developed the first automatic IC tester - Model 4000. It too consisted of various constant current and voltage sources and measuring units. It was programmed from a magnetic disc with a a fixed word format in machine language, and it had the ability to "burst" a series of digital pulses to test the IC functionality. This was the first commercially available IC tester. That was in 1965.

The next commercial tester on the market was the model 553, manufactured by Texas Instruments. Similar in concept to the Fairchild Model 4000, it was programmed with continuous paper tape. But it was the introduction of Model J259 by Teradyne that radically changed the ATE industry. Teradyne coupled a digital computer with the test instrumentation and opened new era of semiconductor ATE in 1967.

Fairchild developed their version of a computer-controlled IC tester; and many other manufacturers of ATE emerged. But it was Teradyne that dominated the ATE marketplace for many years.

As faster devices were designed and as LSI began to emerge, the emphasis shifted from parametric tests to functional tests. This required a high degree of parallelism in the tester design. Teradyne tried to fill the need with their SLOT machine. However, although it was adequate for complex MSI and bipolar LSI, it lacked the sophistication for the emerging MOS-LSI.

Until this time, all ATE was designed with the DUT drive and compare circuits in the tester mainframe. Cables were brought to multiplexers from multiple test tables or stations and multiplexed to the tester mainframe. As testing speeds increased due to higher device data rates, this design became unworkable. The first attempt to solve the problem was again made by Teradyne. The drivers in the test head were mulitplexed to test stations with an independent set of comparators. This transmission-line approach was employed in Model J277, but unfortunately it was a failure as a general purpose logic tester. To achieve this, complex performance boards with more general load switching and parametric switching requirements in the test head were needed.

In 1970 the general purpose test system was pioneered by Fairchild and was called the Sentry Series. It was designed with a full set of drivers and receivers in the testhead. Forcing and measuring took place adjacent to the device, as did the GO/NO-GO voltage decision. The time-related pass/fail decision was still made in the mainframe. An advantage of this design was the accomodation of fast data rates. The Sentry was capable of 10Mhz data rates. Tektronix developed a similar test system, called the Model 3260, which had a 20Mhz data rate. Takeda-Riken's Model T320/60Z was the Japanese answer to a general-purpose test system.

Today the general-purpose test system is characterized by pin electronics(PE) in the testhead, while the dedicated test system usually has a less versatile testhead with specific testhead pins that perform specific test functions.

System architecture also developed over the years. The 1st generation systems were self conatined, with local controller that programmed and sequenced the tests. Later, the 2nd generation systems were developed utilizing a minicomputerto program and control the test instrumentation. This greatly enhanced the capability of testing and data handling. The 3rd generation systems of the 1980's employ distributed architecture. In these systems the local controllers operate the tester, while the powerful central host attends to all data manipulations activities. The host computer may interface with many different testers with local microcomputers. Typical 3rd-generation test systems include the Sentry/Integrator, Xincom, Accutest, Adar/MX-17, Lomac, and Megatest Q2/60. The complex designs of ATE systems continue to handle more complex IC designs.

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