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The other item to note is that leakage is inherently a strong function of the silicon device process generation.

In contrast to pins with leakage specifications, pins with pull-up or pull-down current specifications are expected to conduct a siginificant amount of current. For example, pins with pull-up current specifications of 400uA maximum can typically source -270uA.

What is specified in the data sheet should account for the level of tri-state control made available to the customers for the various leaker devices on the buffers being specified. Since majority of the devices today have some form of on-die termination, the leakage value specified in the datasheet should account for the fact of whether the chip manufacturer provides a capability for the customers (OEM) to disable the on-die termination. With this in mind the pin leakage low/high represent the worst current sourced/sunk with all possible active devices shut-off on the buffer.

The purpose of the leakage testing to screen-out unwanted current paths on high impedance I/O pins to Vss and Vcc adjacent signal pins. The primary construct required for leakage testing is the ability to tri-state output buffers and disable any leakers, pull-up and pull-down active devices on all buffers. The goal is to disable any by-design leakage paths on the buffers. The method to tri-state the by-design leakage paths varies by product.

Traditional leakage test methods put the part into tri-state mode and forces a voltage on the pin under test with the tester parametric measurement unit(PMU). Next, the resultant current flow is measured. Pins and other electrical paths adjacent to the pin under test must be forced to the opposite power supply rail to induce the greatest potential across the various defects leakage paths. For this approach, all buffers need to be connected to a tester pin electronics card.

Furthermore, there are two most common techniques in doing leakage test.