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I would like to share with you the commonly used terminologies in IC Test Development Engineering. Hope this would help to the aspiring Test Engineers and could serve as a refresher to all Test Engineers out there.

1. Test Program - the purpose of a semiconductor test program is to control the test hardware (such us ATE or test loadboard) in a manner that will guarantee that the DUT meets or exceeds all of its design parameters. The design parameters are defined in details from the device specification, commonly known as data sheet. The test program is often segmented into various parts such as DC Tests, functional tests and AC tests. DC testing verifies voltage and current parameters. Functional testing verifies correct operation of the various logical functions of the device. AC testing verifies that the device can perform the logical operations with specified timing constraints.

2. Input Pin - a device pin that acts as a buffer between external signals and the internal logic of a device. The input senses the voltage which is applied to it and transmits a logic 0 or logic 1 level to the internal logic of the device.

3. Output Pin - a device pin that acts as a buffer between the internal logic of a device and the external environment. An output pin is capable of providing the correct voltages to produce logic 0 or logic 1 level and also supplies the IOL/IOH current. I will explain these terms later.

4. Tri-State Output - a device pin that functions as an output pin but has the added capability of turning off (going to a high impedance state).

5. Bi-directional (I/O) pin - a device pin that functions as an input, an output and also capable of turning-off (going to a high impedance state).

6. Power Pin - a device pin that is connected to a power supply or ground. VDD and VCC are typical examples of a power pins. VSS and ground are also identified as power pins. Power pins have a structure that is different from signal pins.

7. Pin Electronics - circuitry located in the test head that is used to supply input signals to the DUT and receive output signals from the DUT. The pin electronics are also called PE cards.

8. Drivers - the circuitry on the pin PE card which supplies the logic 0 and logic 1 levels to the DUT. A pin is said to be driven if the test system driver applies a voltage to it.

9. Signal Format - the wave shape of an input signal supplied by the pin electronics driver circuitry.

10. Comparators - the circuitry located on the pin electronics card which senses the logic 0 and logic 1 levels from the DUT. The comparators are used during functional testing.

11. Output Sampling - the point in time at which the output signal of a DUT will be evaluated. The comparator circuitry will comparethe output voltage to a pre-defined logic 1 or logic 0 level. The test system(ATE) will then make a pass or fail decision (commonly called binning).

12. Output Mask - a method of enabling or disabling an output comparison for a tester channel during a functional test.

13. Dynamic Loads - the circuitry located on the pin electronics card which acts as a load and can be programmed to supply positive and negative currents. The dynamic load are also reffered to as programmable current loads.

14. VREF - the reference voltage associated with the dynamic loads. It controls the switching point of IOL and IOH currents.

15. PMU - precision measurements unit, also called parametric measurements unit is used to make accurate DC measurements. It is capable of forcing voltage and measuring current or vice versa.

16. Clamps - hardware which limits the amount of voltage or current that is supplied by the test system during a test. Clamps are used to protect the test operator, the test hardware and the DUT.

17. Sink - term used to describe current flow from the test system into a device output pin(positive current). When an output is in the logic 0 state it can accept current from the test system which will flow through the device to ground.

18. Source - term used to describe current flow from a device output pin into the test system(negative current). When an output is in the logic 1 state it can supply current which will flow from the DUT into the test system.

19. DPS - device power supplies are used to supply voltage & current directly to the DUT. The VDD(power) pin of the DUT will usually be connected to a DPS.

20. Test Cycle - the time duration of one test vector execution. It is based on the operating frequency of the DUT. It can be determined by the formula: Cycle = 1/frequency. It is also known as period.

21. Test Vectors - a representation of the states of inputs and outputs for the various logical functions that the device is designed to perform. Input data is supplied to the DUT by the test system. Output vector data is compared against the response from the output pins of the DUT.
Test vectors are also called test patterns or truth tables. They are often represented as a sequence of ones and zeroes or other characters which represent logical levels.

22. Vectory memory - a high speed memory which stores test vector information. Vector memory may also be called pattern memory.

23. FDATA - formatted vector data (logic 1s and 0s) combined with timing and signal format information.

24. Tester Channel - circuitry on the pin electronics card which applies and/or process voltage, current and timing for one DUT pin. Also called tester pin.

25. VIH - voltage in high is the voltage value applied to an input when when applyinga logic 1. The VIH value represents the minimum guaranteed voltage value that can be applied to an input and still be recognized as a logic 1 by the DUT.

26. VIL - voltage in low is the voltage value applied to an input when applying a logic 0. The VIL value represents the maximum guaranteed voltage value that can be applied to an input and still be recognized as a logic 0 by the DUT circuitry.

27. IIH - input leakage high is the maximum amount of current that is allowed to flow into an input when a low voltage value is forced onto the pin.

28. VOH - voltage out high is the voltage value produced by an output when driving a logic 1. The VOH represents the minimum guaranteed voltage value tha will be produced by the output when driving out logic 1.

29.VOL - voltage out low is the voltage value produced by an output when drving a logic 0.
The VOL represents the maximum guaranteed voltage value that will be produced by the output when driving out logic 0.

30. IOH - current out high is the amount of current that an output must source when driving a logic 1. The output must be capable of supplying the specified IOH current while maintaining the correct VOH voltage.

31. IOL - current out low is the amount of current that an output must sink when driving a logic 0. The output must be capable of accepting the specified IOL current while maintaining the correct VOL voltage.

32. IOZH -output high impedance leakage current high is the maximum amount of current that is allowed to flow when a high voltage is applied to a bi-directional or tri-state pin, and the pin is in the off or high Z-state.

33. Gross Testing - performing a test with relaxed conditions (levels and timings) usually made to verify if the device is "functionally alive" without regards to the test specification.

34. Wafer Sort - testing of individual devices(dice) when they are still in wafer form. This is the first attempt at separating the good die from the bad.

35. Package/Final Test - wafers are cut into individual die and each die is then assembled into package form (dual-inline package, QFP, BGA, flip chip, etc). The package device is then tested to ensure that the assembly process was correctly performd and to verify that the device still meets its design specifications.

36. QA Test - quality assurance testing is performed on a sample basis to ensure that the package test was performed correctly.

37. Binning - a means of categorizing or sorting the tested devices into their appropriate groupings, either hardware or software bins.

38. Preconditioning - setting a device into the proper logic state so that a test may then be performed. A functional vector sequence is often required in order to prepare the DUT for a DC test.

39. Static - this term indicates that the DUT is in a non-active condition, no input or output signals are changing.

40. Dynamic - a term used to indicate that the DUT is actively changing states, dynamic tests are associated with executing functional test vectors.

41. I/O Switching -the DUT alternates between receiving data from the test system (reading data) and applying data to the test system(writing data). The same pin or set of pins functions as both inputs and outputs.

42. Bus contention - a condition that exists when the test system and the DUT are simultaneously driving voltage into the same tester channel.

43. Hot Switching - occurs when a relay is opened while current is flowing through it, or when current immediately begins to flow after a relay is closed (i.e. when the two terminals of a relay are at different voltages when the relay is closed). Opening or closing a relay while current is flowing throught it may result in damage to the relay. This can be avoided through careful test programming/coding.

44. Latch Up - a high current conditions which exists within a CMOS device caused by applying an improper voltage level to a signal pin or by an improper voltage applied to VDD or ground. This condition can weaken the device or cause a catastrophic failure.

45. Glitch - when a signal level abruptly change its voltage (an/or logic) level for a very short time. Sometimes called spike.

That's the most commonly used terms in test engineering or test development engineering activities.